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Silicon Labs /EFM32PG22C200F512IM32 /USART1_NS /IRCTRL

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Interpret as IRCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IREN)IREN 0 (ONE)IRPW 0 (DISABLE)IRFILT

IRPW=ONE, IRFILT=DISABLE

Description

No Description

Fields

IREN

Enable IrDA Module
IRPW

IrDA TX Pulse Width

0 (ONE): IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1

1 (TWO): IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1

2 (THREE): IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1

3 (FOUR): IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1
IRFILT

IrDA RX Filter

0 (DISABLE): No filter enabled

1 (ENABLE): Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data